SI8816EDB www.vishay.com vishay siliconix s15-0346-rev. b, 23-feb-15 1 document number: 62834 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 30 v (d-s) mosfet marking code : xx = ah xxx = date/lot traceability code ordering information: SI8816EDB-t2-e1 (lead (pb) -free and halogen-free) features ? trenchfet ? power mosfet ? ultra small 0.8 mm x 0.8 mm outline ? ultra thin 0.4 mm max. height ? typical esd protection 1700 v (hbm) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ?load switch ?ovp switch ? high speed switching ?dc/dc converters ? for smart phones, tablet pcs, and mobile computing notes a. surface mounted on 1" x 1" fr4 board with full copper, t = 5 s. b. surface mounted on 1" x 1" fr4 board with minimum copper, t = 5 s. c. refer to ipc/jedec ? (j-std-020), no manua l or hand soldering. d. maximum under steady state conditions is 185 c/w. e. maximum under steady stat e conditions is 330 c/w. product summary v ds (v) r ds(on) ( ) max. i d (a) a q g (typ.) 30 0.109 at v gs = 10 v 2.3 2.4 nc 0.116 at v gs = 4.5 v 2.3 0.123 at v gs = 3.7 v 2.2 0.142 at v gs = 2.5 v 2.0 micro foot ? 0.8 x 0.8 back s ide view 1 0.8 mm 0.8 mm xxx xx bump s ide view 1 g 4 d s 3 s 2 1 g s n-channel mosfet s d g absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) t a = 25 c i d 2.3 a a t a = 70 c 1.9 a t a = 25 c 1.5 b t a = 70 c 1.2 b pulsed drain current (t = 300 s) i dm 8 continuous source-drain diode current t a = 25 c i s 0.7 a t a = 25 c 0.4 b maximum power dissipation t a = 25 c p d 0.9 a w t a = 70 c 0.6 a t a = 25 c 0.5 b t a = 70 c 0.3 b operating junction and storage temperature range t j , t stg -55 to 150 c soldering recommendations (peak temperature) c 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, d t 5 s r thja 105 135 c/w maximum junction-to-ambient b, e 200 260
SI8816EDB www.vishay.com vishay siliconix s15-0346-rev. b, 23-feb-15 2 document number: 62834 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not su bject to production testing. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 - - v v ds temperature coefficient v ds /t j i d = 250 a -30- mv/c v gs(th) temperature coefficient v gs(th) /t j --3.2- gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.6 - 1.4 v gate-source leakage i gss v ds = 0 v, v gs = 4.5 v - - 0.1 a v ds = 0 v, v gs = 12 v - - 1 zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v - - 1 v ds = 30 v, v gs = 0 v, t j = 55 c - - 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 10 - - a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 1 a - 0.087 0.109 v gs = 4.5 v, i d = 1 a - 0.093 0.116 v gs = 3.7 v, i d = 1 a - 0.096 0.123 v gs = 2.5 v, i d = 0.5 a - 0.110 0.142 forward transconductance a g fs v ds = 10 v, i d = 1 a - 10 - s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz - 195 - pf output capacitance c oss -35- reverse transfer capacitance c rss -15- total gate charge q g v ds = 15 v, v gs = 10 v, i d = 1 a - 4.4 8 nc v ds = 15 v, v gs = 4.5 v, i d = 1 a -2.44.5 gate-source charge q gs -0.35- gate-drain charge q gd -0.55- gate resistance r g f = 1 mhz - 4 - turn-on delay time t d(on) v dd = 15 v, r l = 15 i d ? 1 a, v gen = 4.5 v, rg = 1 -1530 ns rise time t r -2040 turn-off delay time t d(off) -2040 fall time t f -1020 turn-on delay time t d(on) v dd = 15 v, r l = 15 i d ? 1 a, v gen = 10 v, r g = 1 -510 rise time t r -1020 turn-off delay time t d(off) -1530 fall time t f -510 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - - 0.7 a pulse diode forward current i sm --8 body diode voltage v sd i s = 1 a, v gs = 0 v - 0.75 1.2 v body diode reverse recovery time t rr i f = 1 a, di/dt = 100 a/s, t j = 25 c -1630ns body diode reverse recovery charge q rr -612nc reverse recovery fall time t a - 13.5 - ns reverse recovery rise time t b -2.5-
SI8816EDB www.vishay.com vishay siliconix s15-0346-rev. b, 23-feb-15 3 document number: 62834 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) gate current vs. gate-source voltage output characteristics on-resistance vs. drain current gate current vs. gate-source voltage transfer characteristics capacitance vs. drain-to-source voltage 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 3 6 9 12 15 18 i gss - g ate current (ma) v gs - g ate- s ource voltage (v) t j = 25 c 0 3 6 9 12 15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i d - drain current (a) v d s - drain-to- s ource voltage (v) v gs = 1.5 v v gs = 2 v v gs = 5 v thru 2.5 v v gs = 1 v 0.06 0.09 0.12 0.15 0.18 0 2 4 6 8 r d s (on) - on-re s i s tance () i d - drain current (a) v gs = 3.7 v v gs = 2.5 v v gs = 4.5 v v gs = 10 v 10 -2 10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 0 3 6 9 12 15 18 i gss - g ate current (a) v gs - g ate-to- s ource voltage (v) t j = 150 c t j = 25 c 0 2 4 6 8 0.0 0.5 1.0 1.5 2.0 2.5 i d - drain current (a) v gs - g ate-to- s ource voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 50 100 150 200 250 0 5 10 15 20 25 30 c - capacitance (pf) v d s - drain-to- s ource voltage (v) c i ss ss ss
SI8816EDB www.vishay.com vishay siliconix s15-0346-rev. b, 23-feb-15 4 document number: 62834 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) gate charge on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage source-drain diode forward voltage threshold voltage single pulse power (junction-to-ambient) 0 2 4 6 8 0 1 2 3 4 v gs - g ate-to- s ource voltage (v) q g - total g ate charge (nc) v d s = 24 v v d s = 7.5 v v d s = 15 v i d = 1 a 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 - 50 - 25 0 25 50 75 100 125 150 r d s (on) - on-re s i s tance (normalized) t j - junction temperature ( c) v gs = 10 v, 4.5 v, 3.7 v, 2.5 v; i d = 1 a 0.05 0.10 0.15 0.20 0.25 0.30 0 1 2 3 4 5 r d s (on) - on-re s i s tance () v gs - g ate-to- s ource voltage (v) t j = 125 c t j = 25 c i d = 1 a 0.1 1 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s - s ource current (a) v s d - s ource-to-drain voltage (v) t j = 150 c t j = 25 c 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 - 50 - 25 0 25 50 75 100 125 150 v gs (th) (v) t j - temperature ( c) i d = 250 a 0 2 4 6 8 10 12 14 power (w) time ( s ) 10 1000 0.1 0.01 0.001 100 1
SI8816EDB www.vishay.com vishay siliconix s15-0346-rev. b, 23-feb-15 5 document number: 62834 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) safe operating area, junction-to-ambient current derating* power derating note when mounted on 1" x 1" fr4 with full copper. * the power dissipation p d is based on t j (max.) = 150 c, using junction-to- ambient thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the cu rrent rating, when this rating falls below the package limit. 0.01 0.1 1 10 0.1 1 10 100 i d - drain current (a) v d s - drain-to- s ource voltage (v) * v gs > minimum v gs at which r d s (on) i s s pecified 10 s 100 m s 1 s , 10 m s 100 s limited by r d s ( on ) * 1 m s t a = 25 c bvd ss limited dc 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 150 i d - drain current (a) t a - ambient temperature ( c) 0.0 0.2 0.4 0.6 0.8 25 50 75 100 125 150 t a - ambient temperature (c) power di ss ipation (w)
SI8816EDB www.vishay.com vishay siliconix s15-0346-rev. b, 23-feb-15 6 document number: 62834 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient (on 1" x 1" fr4 board with maximum copper) normalized thermal transient impedance, junction-to- ambient (on 1" x 1" fr4 board with minimum copper) vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62834 . 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 sq uare wave pul s e duration ( s ) normalized effective tran s ient thermal impedance 1 0.1 0.01 t 1 t 2 note s : p dm 1. duty cycle, d = 2. per unit ba s e=r thja = 185 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s urface mounted duty cycle = 0.5 s ingle pul s e 0.02 0.05 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 sq uare wave pul s e duration ( s ) normalized effective tran s ient thermal impedance 1 0.1 0.01 t 1 t 2 note s : p dm 1. duty cycle, d = 2. per unit ba s e=r thja = 330 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s urface mounted duty cycle = 0.5 s ingle pul s e 0.02 0.05
package information www.vishay.com vishay siliconix revision: 16-feb-15 1 document number: 69442 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 micro foot ? : 4-bump (0.8 mm x 0.8 mm, 0.4 mm pitch) notes (1) laser mark on the backside surface of die (2) bumps are 95.5 % sn,3.8 % ag,0.7 % cu (3) i is the location of pin 1 (4) b1 is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. (5) non-solder mask defi ned copper landing pad. note a. use millimeters as the primary measurement. dim. millimeters a inches min. nom. max. min. nom. max. a 0.328 0.365 0.402 0.0129 0.0144 0.0158 a1 0.136 0.160 0.184 0.0053 0.0062 0.0072 a2 0.192 0.205 0.218 0.0076 0.0081 0.0086 b 0.200 0.220 0.240 0.0078 0.0086 0.0094 b1 0.175 0.0068 e 0.400 0.0157 s 0.160 0.180 0.200 0.0062 0.0070 0.0078 d 0.720 0.760 0.800 0.0283 0.0299 0.0314 k 0.040 0.070 0.100 0.0015 0.0027 0.0039 xxx ak mark on backside of die d d s e s s e s 4x ? b s s g d note 4 a a1 a2 bump note 2 b k e e 4-? 0.205 to 0.225 note 5 solder mask ~? 0.215 b1 ecn: t15-0053-rev. a, 16-feb-15 dwg: 6033
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